61 intptr_t
cpu_AtomicAdd(
volatile intptr_t* location, intptr_t increment);
72 bool cpu_CAS(
volatile intptr_t* location, intptr_t expected, intptr_t newValue);
80 inline bool cpu_CAS(
volatile T* location,
T expected,
T new_value)
82 return cpu_CAS((
volatile intptr_t*)location, (intptr_t)expected, (intptr_t)new_value);
93 #if MSC_VERSION && ARCH_X86_X64 95 #elif GCC_VERSION && ARCH_X86_X64 96 __asm__ __volatile__(
"rep; nop" : : :
"memory" );
100 #endif // #ifndef INCLUDED_CPU int64_t i64
Definition: types.h:35
void cpu_Test()
Definition: cpu.cpp:66
bool cpu_CAS(volatile intptr_t *location, intptr_t expected, intptr_t newValue)
atomic "compare and swap".
Definition: aarch64.cpp:36
intptr_t cpu_AtomicAdd(volatile intptr_t *location, intptr_t increment)
add a signed value to a variable without the possibility of interference from other threads/CPUs...
Definition: aarch64.cpp:31
i64 Status
Error handling system.
Definition: status.h:169
#define T(string_literal)
Definition: secure_crt.cpp:77
const Status CPU_UNKNOWN_OPCODE
Definition: cpu.h:36
const Status CPU_FEATURE_MISSING
Definition: cpu.h:35
Introduction
Definition: debug.h:407
const Status CPU_UNKNOWN_VENDOR
Definition: cpu.h:37
bool cpu_CAS64(volatile i64 *location, i64 expected, i64 newValue)
Definition: aarch64.cpp:41
const char * cpu_IdentifierString()
Definition: aarch64.cpp:46
void cpu_Pause()
pause in spin-wait loops, as a performance optimisation.
Definition: cpu.h:91